A fundamental design challenge in creating a memory cell of an electrically erasable programmable read only memory (EEPROM) device is to use a controllable and reproducible electrical effect that has sufficient non-linearity so that the memory cell (1) can be written to (or erased) at one voltage in less than one millisecond (1 ms) and can be read at another voltage, and (2) the data within the memory cell must remain unchanged for more than ten (10) years.
Prior art stacked/split gate EEPROM technology requires (1) special multi-polysilicon materials, (2) different gate oxide thicknesses, and (3) modified doping profiles. These prior art requirements create process complexity and high cost when embedded into a complementary metal oxide semiconductor (CMOS) process.
FIG. 1 illustrates a schematic diagram of a prior art memory cell 100 of a single poly erasable programmable read only memory (EEPROM) device. Memory cell 100 comprises one P-channel metal oxide semiconductor (PMOS) transistor 110 and one P-channel metal oxide semiconductor (PMOS) capacitor 120. The PMOS capacitor 120 is formed by connecting together the source, drain and substrate of a PMOS transistor. A cross sectional view 200 of the memory cell 100 is shown in FIG. 2.
The PMOS transistor 110 may be referred to as PMOS program transistor 110. The PMOS capacitor 120 may be referred to as PMOS control capacitor 120. The gate of the PMOS program transistor 110 and the gate of the PMOS control capacitor 120 are connected together (i.e., shorted together) and are isolated from the other active elements. The shorted gates of the PMOS program transistor 110 and the PMOS control capacitor 120 are collectively referred to as a “floating gate” 130. Charges (in amounts that represent either a zero (0) representation or a one (1) representation) may be written to the floating gate 130. In order to avoid well bias interference, the PMOS program transistor 110 and the PMOS control capacitor 120 are each located in a separate N well.
The prior art memory cell 100 is written to by injecting drain avalanche hot electrons into the floating gate 130. For PMOS operation (as shown in FIG. 1 and in FIG. 2) low voltage is applied to the control gate and drain of PMOS control capacitor 120 and high voltage is applied to the source/well of PMOS program transistor 110. The channel of PMOS program transistor 110 is turned on and hot electrons are generated at the high electric field region at the drain junction (designated “Vinj” in FIG. 1). With positive voltage on the control gate of PMOS control transistor 120, some hot electrons with high energy will pass through the silicon-silicon dioxide (Si—SiO2) potential barrier and be injected into the floating gate 130.
The prior art memory cell 100 is erased by applying a high voltage to the control gate of the PMOS control transistor 120 and by grounding the drain and source of the PMOS program transistor 110. Electrons on the floating gate 130 will pass through the gate oxide between the floating gate 130 and the control gate of the PMOS control capacitor 120 by Fowler-Nordheim (FN) tunneling process and go to the substrate.
During programming, most control gate voltage should be coupled between the floating gate 130 and the drain/source of the PMOS program transistor 110 to facilitate electron injection to the floating gate 130 but not further to the control gate of the PMOS control transistor 120. This requires the capacitance between the floating gate 130 and the control gate to be large. On the other hand, during the erase procedure, more control gate voltage should be coupled between the floating gate 130 and the control gate, so that electrons can tunnel from the floating gate 130 to the substrate by the Fowler-Nordheim (FN) tunneling process. This requires the capacitance between the floating gate 130 and the control gate to be small.
These two contradictory requirements for the control gate capacitance during the program procedure and the erase procedure leave a narrower operation window. This results in poor data retention and slower speeds for an EEPROM that comprises one PMOS program transistor and one PMOS control capacitor.
To improve the operational speed and data retention for a single poly EEPROM device, EEPROM designers have sometimes placed an additional capacitor in the basic memory cell. This approach has one large capacitor for the programming operation and one small capacitor for the erase operation. Capacitor coupling techniques are used to achieve a favorable electric field for both the programming operation and the erase operation.
The floating gate of an added capacitor has to be filled with hot electrons. Hot electrons that pass through gate oxide will create oxide damage. Oxide damage degrades the endurance of a memory cell. Endurance is measured by how many program/erase cycles the gate oxide can tolerate before unacceptable damage occurs. Therefore, one major drawback to adding an extra capacitor is that it degrades EEPROM memory cell endurance performance.
Another drawback to adding an extra capacitor is that it significantly increases the size of the basic memory cell. This significantly lowers the EEPROM density. Additional chip area is required for the extra capacitors. This increases the cost.
Another drawback of prior art CMOS EEPROM technology is the speed of the programming procedure. The programming procedure is carried out by utilizing drain avalanche hot electrons. Because the efficiency of generating and injecting the drain avalanche hot electrons is low, programming times are relatively long. The programming time is usually one hundred milliseconds (100 ms) or longer. Even the improved coupling provided by using additional capacitors only reduces the programming time to about twenty milliseconds (20 ms).
To improve the operational speed and data retention for the memory cells of EEPROM devices, EEPROM designers have developed approaches that rely on a technique that is referred to as “Source-Side (channel hot electron) Injection” (“SSI”). An example of this approach is a split gate, floating gate memory cell developed and patented by Silicon Storage Technology, Inc. called SST CMOS SuperFlash™ EEPROM Cell. SuperFlash™ is a trademark of Silicon Storage Technology, Inc.
A schematic representation of the prior art SST CMOS SuperFlash™ EEPROM Cell 300 is shown in FIG. 3. The memory cell 300 comprises a memory transistor 310 and a select transistor 320. The gate of the memory transistor 310 comprises a floating gate 330 and a control gate 340. The gate of the select transistor 320 comprises a select gate 350. The control gate 340 and the select gate 350 are in fact one and the same in a “split” gate configuration.
The channel of the memory transistor 310 (and hence the current through it) is controlled by the combination of the floating gate 330 and the control gate 340. Depending upon the amount of charge that is stored on the floating gate 330, the memory transistor 310 is in either a high threshold state or a low threshold state.
FIG. 4 shows a schematic representation of a cross section 400 of the memory transistor 310 along the bit line direction. FIG. 4 is taken from a scanning electron microscope (SEM) micrograph of a cross section of memory transistor 310. The memory transistor 310 comprises source 410, channel 420 and drain 430.
The floating gate 330 is formed of a first layer of polysilicon (referred to as “Poly 1”). The control gate 340 is formed of a second layer of polysilicon (referred to as “Poly 2”). The floating gate 330 and the control gate 340 are covered with a gate oxide 440. The gate oxide 440 is covered with another oxide layer 450, which in turn is covered with yet another oxide layer 460.
The floating gate 330 is separated from the source 410 and from the channel 420 by approximately one hundred fifty Ångstroms (150 Å) of gate oxide 440. The control gate 340 is separated from the channel 420 by approximately four hundred Ångstroms (400 Å) of gate oxide 440. The end of the floating gate 330 nearest to the control gate 340 is separated from the sidewall of the control gate 340 by approximately 400 hundred Ångstroms (400 Å) of gate oxide 440. The top of the floating gate 330 is separated from the control gate 340 in the vertical direction by approximately two thousand Ångstroms (2000 Å) of gate oxide 440. A tunneling injector 470 is formed on the edge of the first layer of polysilicon (“Poly 1”) of floating gate 330.
The memory cell 300 that comprises memory transistor 310 and select transistor 320 erases by using Fowler-Nordheim (“FN”) tunneling from floating gate 330 to control gate 340. The floating gate poly oxidation process provides a uniform field enhanced tunneling injector along the edges of the floating gate 330. This is a key feature of the SST CMOS SuperFlash™ EEPROM Cell 300. The presence of the corner enhanced electric field decreases the voltage that is required to perform the erase function.
For example, during the erase procedure, the source 410 and the drain 430 are grounded and the voltage on the control gate 340 is increased to about fifteen volts (15 V). The low coupling ratio between the control gate 340 and the floating gate 330 provides a significant voltage across the interpoly gate oxide 440 between the Poly 1 of the floating gate 330 and the Poly 2 of the control gate 340. A local high electric field is generated primarily along the edge of the tunneling injector 470.
Charge transfer occurs between the control gate 340 and the floating gate 330. The charge transfer is eventually limited by the accumulation of positive charge on the floating gate 330. That is, the positive charge on the floating gate 330 increases the floating gate voltage until there is insufficient voltage across the interpoly gate oxide 440 to sustain Fowler-Nordheim tunneling.
The removal of negative charge from the floating gate 330 leaves a net positive charge on the floating gate 330. The resulting positive charge on the floating gate 330 decreases the threshold voltage of the memory cell 300 so that the memory cell 300 will conduct during a read and give a value of one (“1”). In this manner the memory cell 300 is programmed using a high efficiency Source-Side (channel hot electron) Injection (“SSI”).
During the programming procedure, a voltage that is approximately equal to the threshold voltage (“Vt”) of the select transistor 320 is placed on the control gate 340. This is sufficient to turn on the channel 420 under the select portion of the control gate 340. The drain 430 is held to the Vss voltage (the ground voltage) if the memory cell 300 is to be programmed. The drain 430 is held to the Vdd voltage (the power supply voltage) is the memory cell 300 is inhibited from being programmed.
The drain voltage (i.e., the voltage at drain 430) is transferred across the select channel because of the voltage on the control gate 340. The source voltage (i.e., the voltage at source 410) is held to twelve volts (12 V). The source to drain voltage differential generates hot channel electrons. The source voltage is capacitatively coupled to the floating gate 330. The electric field between the floating gate 330 and the channel 420 sweeps the channel hot electrons that cross the silicon-silicon dioxide (Si—SiO2) barrier of three and two tenths electron volts (3.2 eV) to the floating gate 330.
The structure of memory cell 300 has several major drawbacks. One drawback is that in order to get a sufficiently high coupling from the source 410 to the floating gate 330 during the programming procedure, the lateral extent of the source 410 must have a significant amount of overlap with the floating gate 330. Furthermore, the source 410 must be deep enough to tolerate the high voltage that must be applied (typically, twelve volts (12 V) as previously mentioned).
The lateral extent of the significant overlap of the source 410 with the floating gate 330 is shown in FIG. 4. The requirement a large source 410, the size of the overlap between the source 410 and the floating gate 330, and the size of the channel 420 under the control gate 340 make the size of the bitcell greater than thirteen square units of feature size (13 F2). A typical feature size (F) may be thirty five hundredths of a micron (0.35 μm).
Another drawback is that the fabrication process for the memory cell 300 is complicated. The fabrication process for the memory cell 300 requires the creation of a special injector profile for the tunneling injector 470 and a very thick layer (approximately 2000 Å) of interpoly gate oxide 440 on top of the floating gate 330. Furthermore, a buried high voltage drain 430 is required that is not self-aligned to the floating gate 330. A relatively thick layer of gate oxide 440 (approximately 150 Å) must be formed under the floating gate 330 to separate the floating gate 330 from the source 410 and the channel 420. Lastly, a relatively thick layer of gate oxide 440 (approximately 400 Å) must be formed under the control gate 340 to separate the control gate 340 from the channel 420.
Therefore, there is a need in the art for an improved system and method for providing an improved high density electrically erasable programmable read only memory (EEPROM) device. In particular, there is a need in the art for an improved system and method for providing low voltage high density multi-bit storage flash memory for an electrically erasable programmable read only memory (EEPROM) device.
Before undertaking the Detailed Description of the Invention below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like.
Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior uses, as well as to future uses, of such defined words and phrases.